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SAM: Difference between revisions

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Line 51: Line 51:
|-  
|-  
|FFC8
|FFC8
|
|F1CLR
|
|
|
|
Line 61: Line 61:
|-  
|-  
|FFCA
|FFCA
|
|F2CLR
|SAM F2 bit clear  
|SAM F2 bit clear  
|
|
Line 71: Line 71:
|-  
|-  
|FFCC
|FFCC
|
|F3CLR
|
|
|
|
|-  
|-  
|FFCD
|FFCD
|
|F3SET
|  
|  
| $1000
| $1000
|-  
|-  
|FFCE
|FFCE
|
|F4CLR
|  
|  
|
|
|-  
|-  
|FFCF
|FFCF
|
|F4SET
|  
|  
| $2000
| $2000
|-  
|-  
|FFD0
|FFD0
|
|F5CLR
|  
|  
|
|
|-  
|-  
|FFD1
|FFD1
|
|F5SET
|  
|  
| $4000
| $4000
|-  
|-  
|FFD2
|FFD2
|
|F6CLR
|  
|  
|  
|  
|-  
|-  
|FFD3
|FFD3
|
|F6SET
|  
|  
| $8000
| $8000

Revision as of 22:35, 4 May 2013

The SAM or Synchronous Address Multiplexer is a chip that controls access to RAM memory by the 6809 CPU and the VDG (Video Display Generator).

SAM Registers

Address Shorthand name Function Effect
FFC0 V2CLR SAM V2 bit clear
FFC1 V2SET SAM V2 bit set
FFC2 V1CLR SAM V1 bit clear
FFC3 V1SET SAM V1 bit set
FFC4 V0CLR SAM V0 bit clear
FFC5 V0SET SAM V0 bit set
FFC6 F0CLR SAM F0 bit clear
FFC7 F0SET SAM F0 set bit add $200 to video offset
FFC8 F1CLR
FFC9 F1SET SAM F1 set bit add $400 to video offset
FFCA F2CLR SAM F2 bit clear
FFCB F2SET SAM F2 set bit add $800 to video offset
FFCC F3CLR
FFCD F3SET $1000
FFCE F4CLR
FFCF F4SET $2000
FFD0 F5CLR
FFD1 F5SET $4000
FFD2 F6CLR
FFD3 F6SET $8000