MediaWiki:Sitenotice:
2025-12-29: I have restored the wiki to a backup from the end of November. Starting in September 2025, accesses went form the 800MB-1.2GB range per month to 26GB in September, 42GB in October, and 70GB in November with most accesses originating from China. As soon as I realized what was causing all the access problems in November, I shut it down (it had reached 36GB by then) behind a password/login screen. The database had gotten corrupted, and I tried a restore from just before the spike in access but that didn't work. Thus, end of November. I still have the other daily backups so if there were any important additions in December, let me know and maybe they can be recovered. - Allen H.

SAM: Difference between revisions

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Sarrazip (talk | contribs)
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Fixed the naming of the V register bits.
 
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Line 8: Line 8:
! Shorthand name
! Shorthand name
! Function
! Function
! Effect
|-  
|-  
|FFC0
|FFC0
|V2CLR
|V0CLR
|SAM V2 bit clear
|SAM V0 bit clear
|
|-  
|-  
|FFC1
|FFC1
|V2SET
|V0SET
|SAM V2 bit set
|SAM V0 bit set
|
|-  
|-  
|FFC2
|FFC2
|V1CLR
|V1CLR
|SAM V1 bit clear
|SAM V1 bit clear
|
|-  
|-  
|FFC3
|FFC3
|V1SET
|V1SET
|SAM V1 bit set  
|SAM V1 bit set  
|
|-  
|-  
|FFC4
|FFC4
|V0CLR
|V2CLR
|SAM V0 bit clear
|SAM V2 bit clear
|
|-  
|-  
|FFC5
|FFC5
|V0SET
|V2SET
|SAM V0 bit set  
|SAM V2 bit set  
|
|-  
|-  
|FFC6
|FFC6
|F0CLR
|F0CLR
|SAM F0 bit clear
|SAM F0 bit clear  
|
|-  
|-  
|FFC7
|FFC7
|F0SET
|F0SET
|SAM F0 set bit to add $200 to video offset
|SAM F0 set bit  
|add $200 to video offset
|-  
|-  
|FFC8
|FFC8
|
|F1CLR
|SAM F1 clear bit
|
|
|-  
|-  
|FFC9
|FFC9
|F1SET
|F1SET
|SAM F1 set bit to add $400 to video offset
|SAM F1 set bit  
|add $400 to video offset
|-  
|-  
|FFCA
|FFCA
|F2CLR
|SAM F2 bit clear
|
|
|SAM F2 bit clear
|-  
|-  
|FFCB
|FFCB
|F2SET
|F2SET
|SAM F2 set bit to add $800 to video offset  
|SAM F2 set bit  
|add $800 to video offset  
|-  
|-  
|FFCC
|FFCC
|F3CLR
|SAM F3 bit clear
|
|
|-
|FFCD
|F3SET
|SAM F3 set bit
|add $1000 to video offset
|-
|FFCE
|F4CLR
|SAM F4 bit clear 
|
|
|-  
|-  
|FFCD
|FFCF
|F4SET
|SAM F4 set bit 
| $2000 to video offset
|-
|FFD0
|F5CLR
|SAM F5 bit clear 
|
|
|-
|FFD1
|F5SET
|SAM F5 set bit
|add $4000 to video offset
|-
|FFD2
|F6CLR
|SAM F6 bit clear 
|  
|  
|-
|FFD3
|F6SET
|SAM F6 set bit 
|add $8000 to video offset
|}
|}


Latest revision as of 20:11, 2 August 2015

The SAM or Synchronous Address Multiplexer is a chip that controls access to RAM memory by the 6809 CPU and the VDG (Video Display Generator).

SAM Registers

Address Shorthand name Function Effect
FFC0 V0CLR SAM V0 bit clear
FFC1 V0SET SAM V0 bit set
FFC2 V1CLR SAM V1 bit clear
FFC3 V1SET SAM V1 bit set
FFC4 V2CLR SAM V2 bit clear
FFC5 V2SET SAM V2 bit set
FFC6 F0CLR SAM F0 bit clear
FFC7 F0SET SAM F0 set bit add $200 to video offset
FFC8 F1CLR SAM F1 clear bit
FFC9 F1SET SAM F1 set bit add $400 to video offset
FFCA F2CLR SAM F2 bit clear
FFCB F2SET SAM F2 set bit add $800 to video offset
FFCC F3CLR SAM F3 bit clear
FFCD F3SET SAM F3 set bit add $1000 to video offset
FFCE F4CLR SAM F4 bit clear
FFCF F4SET SAM F4 set bit $2000 to video offset
FFD0 F5CLR SAM F5 bit clear
FFD1 F5SET SAM F5 set bit add $4000 to video offset
FFD2 F6CLR SAM F6 bit clear
FFD3 F6SET SAM F6 set bit add $8000 to video offset
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