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Undercolor/850104/The Data GathererPart II
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UnderColor, Volume 1, Number 4, February 1, 1985
- Title: The Data GathererPart II
- Author: Dennis Kitsz
- Synopsis: A continuing project.
- Page Scans: Link
It's important for a data acquisition system to have readouts . . . usually, a printed copy of the screen at specific intervals, or a continuous printed record of certain data. I have a bias in favor of parallel printers—the kind that accept an entire byte of data at once, print in both directions, and have memory buffers. The Color Computer was designed for a serial printer, which accepts only one bit at a time and, as a consequence, tends to print more slowly. Parallel printers for data acquisition can be very small and inexpensive (20-column thermal printers can be had for under $50), whereas serial printers cost $150 and up.
Those biases inclined me to design a standard Centronics-style parallel printer port as part of the system. Of course this parallel port can be used for any kind of digital input/output (including system expansion and the inclusion of megabyte-size "RAMdisks"). But, as designed here, it’s a simple parallel printer port.
A modern parallel printer normally has an eight-bit output (for ASCII letters, numbers and symbols as well as graphics); it requires an electronic pulse (called a strobe) to indicate to the printer that a printable character has been sent; and it provides up to four "busy" signals so the software knows when to make the next printable character available. In the Data Gatherer, 8-bit data, strobe, and one busy are used.
The final feature of a data acquisition system is an operating system. . . not one that depends on a user to load a tape,
not even one that tries to load and run an environmentally sensitive file, but rather one that has the operating system stored in a stable read-only memory (ROM). The Data Gatherer has its own operating system (DGOS).
DGOS is stored in an erasable, programmable ROM (EPROM). Its subroutines include data input and output, channel selection, D/A conversion, A/D conversion, parallel printer control, clock read and set, and other routines. A special feature is the Basic download-and-run routine.
To use this feature, an 8K or 16K EPROM is programmed with DGOS. The remainder of the EPROM is programmed with the Basic program to be run. The rest is automatic; when the power is turned on, the Color Computer immediately sets up its Basic parameters and initializes the Data Gatherer software. Once initialized, DGOS downloads the Basic program and runs it. A user is needed for a tape system, and disk systems can't take heat or cold. But the DGOS download will survive heat, cold—and power failures. (A complete listing of DGOS will be presented later in this series.)
l mentioned that the Data Gatherer would be compatible with a full-blown Color Computer system, including disks. As it stands, though, the auto-boot from ROM is only provided for in a non-disk system. (For auto-boot from disk, refer to the ongoing eight-part series in The Rainbow by C. Stearman, which offers an outstanding group of "ROMmable" DOS patches.)
Aside from the auto-boot, DGOS will work with a disk system, although a little fancy footwork is necessary to get DGOS in place. Part of what takes place in a Color Computer system is the responsibility of the Synchronous Address Multiplexer (SAM). It takes care of blocking out the computer’s memory into RAM, ROM#0 (Extended Basic), ROM#1 (Color Basic), ROM#2 (Disk Basic), and three small input/output (l/O) blocks. The SAM does this by providing three binary signals called S0, S1 and S2.
By hooking the SAM's S0, S1 and S2 to a 3-to-8 demultiplexer (an integrated circuit that turns three binary signals into eight distinct "select" lines), the memory map can be broken into the eight unique blocks described above. The block for ROM#2 runs from memory location $C000—$FEFF (decimal 49152—65279). Look at the block diagram (last issue's Figure 1) again. At the bottom is a section marked "ROM logic." It turns out that Disk Basic is only an 8K ROM, and needs only addresses $C0O0—$DFFF (decimal 49152—57343). The rest is unused. It would seem reasonable to use the remaining addresses $E000—$FEFF (decimal 57344—65279) for extra user ROMs.
But that is not the case. Since (probably for economic reasons) Radio Shack chose not to add another integrated circuit to decode the disk ROM completely, it appears in identical form at both $C000 and $5000). The space from $E000 on up is effectively wasted.
The ROM logic in the Data Gatherer breaks this memory area into two pieces, routing one to the Radio Shack DOS ($CO00—$DFFF) and the other to DGOS ($E000—$FEFF). So the DGOS subroutines are available to all Color Computer users.
Using The Ports
The A/D and D/A convener system and printer port are accessed using 6821 peripheral interface adapters (PIAs). Because a PIA is a semi-intelligent circuit it can be difficult
to understand. A microprocessor like the 6809 is supposed to be programmable, and its logic seems clear, but I’ve learned that many people (myself once included) are stymied by smart
peripheral chips like the 6821.
Here's a precis. One purpose of a PIA is to read "outside world" digital data into the computer's central processing unit (the 6809 is the Color Computer’s CPU). Its other purpose is to allow the CPU to send digital data to the outside world. The 6809 CPU reads and writes data in 8-bit words, or bytes.
The 6821 PIA has two 8-bit ports, that is, windows to the outside world. You can latch a byte into either port of the PIA, holding it there to control external devices, or you can
input a byte through either port to read external devices.
What is especially useful about the 6821 PIA is that you can latch only part of a byte from the CPU (individual bits) at the port’s output, and use the remaining bits as input to the CPU. Each binary digit of two bytes—16 bits in all- can be used differently . . . as a control line to the outside world, or for information retrieval from the outside world.
The tricky part is configuring the PIA, which means setting up which bits are input, which bits are output, and how the PIA is to respond to special conditions. Those special conditions include interrupts to the CPU and four special input/output lines.
The two eight-bit input/output ports of the PIA are arranged to appear at even-numbered addresses. For example, when a PIA is wired into the Data Gatherer, the input/output ports
for the A/D converter's PIA appear at addresses $FF50 and $FF32. In other words, if data is to be sent to the outside world, it is written to $FF50 or $FF52; data to be received from the outside world is read from $FF50 or $FF52. Configuring $FF50 and $FF52 — choosing whether data in fact will be sent or received — is the job of the PIA's control registers.
The control registers of the PIA are arranged to appear at odd-numbered addresses. In the example of the Data Gatherer, the control registers for the first PIA appear at addresses $FF51 and $FF53. $FF51 is the control register affecting port $FF50; $FF53 is the control register affecting port $FF52.
In the control register, each bit has a separate meaning. Bits 7 and 6 provide information to the CPU about interrupts; bits 0 and 1 provide information to the PIA about interrupts. Bits 5, 4 and 3 control special "CA" outputs from the PIA. All these control bits can be used by the Data Gatherer, but are outside the scope of this article.
Bit 2 opens the door to your commands to the input/output ports. When bit 2 of control register $FF51 is zero, you can tell the PIA which bits of port SFF50 will be used as input, and which bits will be used as output. Here’s the tricky part: When bit 2 of control register $FF51 is one, address $FF50 actually is your input/output port. But when bit 2 of control register $FF51 is zero, address $FF50 merely identifies the direction of the port bits (in or out).
Write 00000000 to control register $FF51 (such as POKE &HFF51,0) and the PIA says, "I am ready for your command. Which way shall the data flow?" Then write the bits to port $FF50 ... 1 = out, 0 = in. Want them all outputs? POKE&HFF50,&HFF (binary 11111111). Want them all inputs? POKE&HFF50,0 (binary 00000000). Want upper half inputs and lower half outputs? POKE&HFF50,&H0F binary (00001111). Want them alternating, half input, half output? POKE&HFF50,&HAA (binary 10101010).
Then, when you’re done identifying the direction, make bit 2 of control register $FF51 become high (00000100) with a command such as POKE &HFF51,4. The PIA says, "I have received your command and the data shall flow as you indicate." Address $FF50 once again becomes the actual port through which data will flow.
The port configuration chart (Figure 1) summarizes this information for both PIAs—a total of four ports and their four complementary control registers. Note that ports $FF50, $FF52 and $FF56 are all used as output in the Data Gatherer, but that port $FF54 is split (two bits input, six bits output). Control registers $FF51 and $FF55 also have a unique use for bit 4, which I'll talk about in the circuit details.
The complete schematic of the Data Gatherer is shown in Figure 2.
U1 is the demultiplexer that breaks down the SCS* block $FF40-$FF5F. $FF40-4F is routed to the clock/disk bank-select circuitry. $FF50-53 is routed to U2, the PIA which controls the digital-to-analog converter. $FF54-57 goes to U3, the PIA which controls the parallel printer port and the analog switch circuitry. $FF58-5B makes its way to the clock/disk bank-select flip-flop control, and $FF5C-5F is a spare select line.
Parts of negative-logic AND gate U8 and inverter U11, plus flip-flop U7, form the clock/disk bank-select control. At power-up, the CPU’s Reset* signal causes flip-flop U7 to make the Q output become 0 and Q* output become 1. When Q=0 and Q*=1 at power-up, the spare chip select $FF40—4F is gated through U12b to form a disk select signal, Disk*. Therefore, the disk drive is available as soon as the system is turned on,
When Swap* (actually port $FF58) occurs together with a write (WR*) from the CPU, the flip-flop latches the level on CPU data line D0. A zero on this line makes flip-flop Q=0 and Q*=1; conversely, a one on this line makes flip-flop Q=1 and Q*=O. When Q=1 and Q* =0, the spare chip select $FF40—4F is gated through U12a to form a clock select signal, CLK*.
The clock/calendar is designed for 8080-style microcomputer signals, which means it expects separate low read (RD*) and low write (WR*). The Color Computer's 6809E has a single line (R/W'). To convert R/W' into separate RD* and WR*, R/W* is provided in normal and inverted (via U11) form, and gated with CLK* through U12c and U12d. The combination—at last—creates WRCLK* and RDCLK*.
The clock itself receives data lines DO—D3 and address lines A0—A3 from the CPU, plus a chip select (CS*, from CLK*). A 32768 Hz oscillator keeps it going, and a combina-
tion of semiconductors provides the battery back-up and recharge.
U15 is the DGOS control of ROM. A combination of inverter U11 and negative-logic AND gate U8 filter the cartridge ROM select line (CTS*) into a high block (for DGOS) and a low block (for the Radio Shack DOS).
PIA U2 sends the 12 bits of data and four bits of address required by D/A converter U4. Note signal CA2, which is set up as an output (refer to Fig. 1) to strobe information into U4 via its chip select (CS*). U4 has a span select, a O—volts adjustment, and a full-scale adjustment. Its output is fed to the non-inverting input of comparator U13.
PIA U3 sends eight bits of data to the parallel printer port. Signal CA2 is used as a printer strobe (STB*) (Fig. 1). Port A, bit 6, is used as a printer ready detect (RDY*), and port A, bit 7, is the output of comparator U13. These are the only two bits set up as inputs in the Data Gatherer system, although the parallel port can be reconfigured as needed for control if a printer is not used.
PIA U3 also controls the selection of one of 16 channels of input to the comparator. Open-collector driver U0 acts as
a level shifter for control of CMOS analog multiplexers U5 and U6. The combinations of A, B, SX and SY determine which input (from 1X0-1X3, 1Y0-1Y3, 2X0-2X3 or 2Y0-2Y3) is allowed to pass through the multiplexers (to Z1 or Z2), eventually feeding the inverting input of comparator U13.
U14, capacitors and zener diodes help stabilize and regulate the user-supplied power source of +/-12 volts, provide a logic supply of +5 volts, and protect the Data Gatherer from over voltage.
Continued . . .
I'll give you a chance to collect some parts and get an idea of how the Data Gatherer and its components work. In the rest of this series, you will learn how to build the Data Gatherer, and what special information you need to know to keep it operating in a stable way (D/A converters can be terribly particular about how you wire them). l have test procedures for you, clock/calendar details, sample applications . . . and the full listing of the Data Gatherer operating system, DGOS. (end)